1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an input/output connection structure of a semiconductor device, such as an internal matching type FET encapsulated in a package.
2. Discussion of the Background
FIG. 1 shows an input/output connection structure in which a power FET chip (hereinafter referred to as FET) is use d as a conventional semiconductor chip.
A FET 1 and a dielectric substrate 5 are fixed to a metal carrier 6. Gate electrode 2 and drain electro de 3 of the FET 1 are connected to an input/output upper electrode 7 of a microstrip line by metal wires 4.
When the characteristic impedance of the input/output upper electrode 7 of the dielectric substrate 5 is set to a desired value, the width of the input/output upper electrode 7, the dielectric constant of the dielectric substrate 5 and the thickness thereof are determined. The chip width of the FET 1 is substantially determined by the saturation power of the FET 1.
For this reason, in most cases, the width of the input/output upper electrode 7 of the dielectric substrate 5 does not coincide with the chip width of the FET 1. More specifically, as the saturation power of the FET 1 is higher, the chip width of the FET 1 is greater than the width of the input/output upper electrode 7.
Therefore, in general, the input/output upper electrode 7 has a wider portion as shown in FIG. 1, to which the metal wires 4 are connected. If the electrode 7 does not have a wider portion, metal wires 4 in edge portions of the FET 1 must be longer than those of a central portion in the width direction of the FET 1.
According to the conventional input/output structure, since the width of the input/output upper electrode 7 is greater in the portion to which the metal wires 4 is connected, the amount of phase shift between points A and B in FIG. 1 is greater in edge portions of the FET 1 than that in a central portion in the width direction of the FET 1. As a result, a phase difference occurs between central and edge portions in the width direction of the gate electrode and drain electrode 2 and 3 of the FET 1, resulting in reduction of the maximum available power gain and power load efficiency of the FET 1. The reduction becomes more considerable, as the saturation power of the FET 1 is increased and the frequency is higher.